Expert Insights - EDA

Robert Vamosi  |  December 16, 2016

Software validation strategies for connected cars

Software validation strategies will become increasingly important as cars become more complex, connected and autonomous.
Ken Brock  |  November 29, 2016

Six ways to exploit the advantages of finFETs

FinFET processes and libraries are maturing, enabling designers to explore the best ways to take advantage of the capabilities of the new transistor design
Topics: EDA - IC Implementation, IP - Selection  |  Tags: , , ,   |  Organizations: ,   |  
Brian Davenport et al  |  November 21, 2016

How functional safety verification helps us build safer cars

Considering the issue of functional safety verification in automotive systems design, within the context of ISO26262
Topics: EDA - Verification  |  Tags: , , ,   |  Organizations:   |  
Paul Dempsey  |  October 3, 2016

Wally Rhines separates the signal from the noise

Mentor's chairman and CEO has dug into why chip sales forecasts often miss the target and suggests some tools for assessing the Internet of Things.
Paul Dempsey  |  September 9, 2016

The inside track on emulation growth

Analysts say there is a $1B market on the horizon. We talk with Mentor's Jean-Marie Brunet about where such a number could come from.
Lauro Rizzatti  |  July 22, 2016

The emulator thrives as verification models mushroom

Emulators have come a long way since their first introduction nearly three decades ago.
Hans van der Schoot  |  July 15, 2016

Team UVM and emulation for testbench acceleration

To verify large, complex designs and meet time-to-market, you must use both simulation and emulation.
Topics: EDA - Verification  |  Tags: , , , ,   |  Organizations:   |  
Anders Nordstrom  |  July 5, 2016

Are you formally secure?

A look at how formal verification strategies can be used to check the security feature of complex SoCs for potential data leakage and data integrity issues
Topics: EDA - Verification  |  Tags: , , ,   |  Organizations:   |  
Anders Nordstrom  |  May 30, 2016

Comparing your design to itself – a crucial part of verification

Sequential equivalence checking can help trap errors introduced by clock gate insertion, uninitialised registers, and X propagation issues.
Andrew Macleod  |  April 26, 2016

Still using Moore’s Law to beat up on the automotive industry?

These days, when it comes to innovation: The car's the star - not the stooge.

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