debug

April 9, 2021
FeatIm-spiral-methodology-bug-hunt

Spiral in on silicon bugs in six formal steps

The best paper winner at DVCon 2021 details a comprehensive methodology for making the best use of formal verification for bug hunting
Article  |  Topics: EDA - Verification  |  Tags: , , ,   |  Organizations: ,
April 6, 2021

The path to full functional monitoring

Joe Sawicki of Siemens EDA recently addressed the main trends in design delivery from architecture to validation to digital twins - and where they may soon take the industry and its products.
August 12, 2020
Tom Anderson is a technical marketing consultant working with multiple EDA vendors, including AMIQ EDA. His previous roles have included vice president of marketing at Breker Verification Systems, vice president of applications engineering at 0-In Design Automation, vice president of engineering at IP pioneer Virtual Chips, group director of product management at Cadence, and director of technical marketing at Synopsys. He holds a Master of Science degree in Computer Science and Electrical Engineering from M.I.T. and a Bachelor of Science degree in Computer Systems Engineering from the University of Massachusetts at Amherst.

How IDEs enable the ‘shift left’ for VHDL

Learn how an IDE offers on-the-fly, auto-correct and informed analysis of VHDL code to speed project quality and delivery.
Expert Insight  |  Topics: EDA - Verification  |  Tags: , , , ,   |  Organizations:
February 14, 2020
P2P-Feb20-featuredimage

A better way to debug P2P results

P2P (point-to-point) resistance is fundamental to IC reliability verification. Handle it more efficiently with detailed, automated path layout analysis.
July 23, 2019
Tom Anderson is a technical marketing consultant working with multiple EDA vendors, including AMIQ EDA. His previous roles have included vice president of marketing at Breker Verification Systems, vice president of applications engineering at 0-In Design Automation, vice president of engineering at IP pioneer Virtual Chips, group director of product management at Cadence, and director of technical marketing at Synopsys. He holds a Master of Science degree in Computer Science and Electrical Engineering from M.I.T. and a Bachelor of Science degree in Computer Systems Engineering from the University of Massachusetts at Amherst.

Correct design and verification coding errors as you type

An IDE designed to catch typographical errors, missing declarations and inconsistent references in your code can hugely reduce your time in debug.
Expert Insight  |  Topics: EDA - IC Implementation, Verification  |  Tags: , , , , , , , , , ,   |  Organizations:
June 18, 2019
Tom Anderson is a technical marketing consultant working with multiple EDA vendors, including AMIQ EDA. His previous roles have included vice president of marketing at Breker Verification Systems, vice president of applications engineering at 0-In Design Automation, vice president of engineering at IP pioneer Virtual Chips, group director of product management at Cadence, and director of technical marketing at Synopsys. He holds a Master of Science degree in Computer Science and Electrical Engineering from M.I.T. and a Bachelor of Science degree in Computer Systems Engineering from the University of Massachusetts at Amherst.

A helping hand for design and verification

Integrated design environments and features within them such as auto-complete deliver valuable efficiencies for input, verification and debut.
Expert Insight  |  Topics: EDA - Verification  |  Tags: , , ,   |  Organizations:
June 11, 2019
Dennis Joseph is a technical marketing engineer supporting Calibre interfaces in the Design-to-Silicon division of Mentor, a Siemens business. His primary focus is the support and enhancement of the Calibre DESIGNrev layout viewer. Dennis received an M.S. in Electrical and Computer Engineering from the University of Florida.

Speed up design and verification with a smaller layout

How to remove or extract portions of a layout for easier, more focused and faster project delivery.
Expert Insight  |  Topics: EDA - IC Implementation, Verification  |  Tags: , , , ,   |  Organizations:
February 6, 2019

Low-power debugging made easy

UPF provides a useful way to describe the power-management strategies that should be applied to a design, but using it introduces a number of challenges during low-power debugging.
Article  |  Topics: EDA - Verification  |  Tags: , ,   |  Organizations:
January 7, 2019
Ashish Darbari is CEO of formal verification consultancy Axiomise.

Doc Formal: Introducing the ADEPT FV flow

Escape formal's narrower definitions with a flow that shows you how to Avoid, Detect, Erase, Prove Absence and Tape Out while avoiding bugs.
Expert Insight  |  Topics: EDA - Verification  |  Tags: , , , , , ,   |  Organizations:
October 5, 2018
Gate-level simulation feature

How to improve throughput for gate-level simulation

Innovative methodologies, strategies and tool features help overcome other inefficiencies in complex but necessary simulations.
Article  |  Topics: EDA - Verification  |  Tags: , , , ,   |  Organizations:

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