You would think that being a perfectionist would be part of the job description for becoming a successful verification engineer, right? But there are times when the ability to overlook imperfections is actually a help, not a hindrance.
Case in point—error waivers. Design rule checks (DRC) are necessary to ensure an IC layout can be successfully manufactured. Engineers must be sure a design is ‘DRC-clean’ as part of the tapeout flow. However, there are times when the check itself is the problem, not the DRC error. For example, rule decks are not usually written from scratch for each new process node, but simply updated and expanded. Occasionally, a design rule needed for a previous node is no longer relevant to the current process, but rather than go to the trouble of clearing out all the old rules, the foundry simply agrees that any results from the associated design rule checks can be waived, meaning they can be ignored and designers do not need to spend any time debugging them. Likewise, maybe there is a rule check that has been proven to be overly restrictive because the condition it checks has been shown to be insignificant in its effect on yield or performance. Waiving any error results may simply be easier and faster than revising the rule deck.
By eliminating these errors from the usual review and correction process, designers can save the time they would have spent analyzing and debugging them . However, before they can ignore these waived results, designers must know they exist. The waivable check results must somehow be identified in the verification flow. Not to worry: Automated waiver management that enables designers to identify and mark error results that can be safely waived has long been a part of EDA physical verification tools .
Then along comes reliability verification, and things change.
Reliability verification waivers
What’s different about reliability check waivers?
Reliability verification enables designers to implement design rules that evaluate a variety of design reliability conditions, including electrostatic discharge (ESD) and latch-up protection, multi-power domain crossing checks, and voltage-aware design rule checking (VA-DRC), as well as any company-defined best practices for reliability design. Unlike DRC, which evaluates physical measurements only, many reliability rule checks require a combination of topological and geometrical information for accurate evaluation. The need to combine physical and circuit data requires a modified approach to the standard physical verification waiver management functionality that is based solely on geometric analysis.
Logic-driven layout analysis
Many reliability rule checks must consider circuit connectivity in conjunction with correlated layout geometrical and electrical data. Implementing these checks requires a tool capable of traversing the design logic (topology) while also accessing these devices’ physical layout properties and their corresponding requirements (layout geometrical/electrical property scheme), as defined by rule checks.
Tools like the Calibre PERC reliability platform employ topological constraints to verify that the correct circuit structures are in place wherever circuit design rules require them. In addition, the Calibre PERC platform can use both netlist and layout (GDS) information simultaneously to perform electrical checks that incorporate both layout-related parameters and circuitry-dependent checks, enabling designers to address these complex verification requirements . This logic-driven layout (LDL) check methodology  provides designers with an automated process for accurate, context-aware reliability verification.
Reliability check waiver processing
Just like DRC waivers management, designers must be able to generate and manage waivers efficiently for reliability rule checks that are safe to ignore. The automated waivers process must accurately identify and apply waivers to the results of these checks, and preserve the waiver data for analysis and validation as needed. What has to change is how the verification flow sets up and runs the reliability verification to incorporate waived check processing. As an example, let’s look at how Calibre PERC handles reliability check waivers.
The solution includes a customized waivers management functionality that enables designers to automatically identify and mark waivable Calibre PERC check errors so they can be excluded from further debugging. While this automated waivers capability was previously limited to topology and geometry waivers that were part of the LDL DRC results , the platform’s automated waiver processing now includes point-to-point (P2P) parasitic resistance and current density (CD) checks.
The Calibre PERC waiver flow is based on the Calibre Auto-Waivers flow  with some specific modifications (Figure 1) to enable the support of LDL, P2P, and CD checks. The waivers are supported for both intellectual property (IP) and full-chip levels. One word of caution: When using the Calibre PERC waiver process, designers must ensure that waivers are only applied to results that are legitimate errors. Waivers are not intended to mask numerous false results that can be produced when using non-optimized reliability rule checks.
Creating a Calibre PERC waivers flow comprises the following basic steps:
- Initiate a Calibre PERC LDL verification run. This run creates a results database containing internal pointers that automatically classify the results files generated from the P2P, CD or DRC flow.
- Mark the results that should be waived (this annotation can be done in the Calibre RVE results viewer).
- Select the geometries to be waived.
- Annotate the waiver cells with the appropriate waiver criteria text. Designers can opt to use the default waiver criteria, or input custom waiver criteria.
- Export the marked geometries to a waivers file (adding a custom name, if desired). The Calibre PERC flow uses this file to automatically detect the waivers type (LDL-DRC, P2P, CD).
- Create a waivers setup file that points to the waivers file.
- Re-run the Calibre LDL verification run with the waivers setup file. This run automatically waives the defined geometric errors and saves the waived result layers in a waived results
- Review the error results and waivers databases.
- If adjustments are needed, revise the waiver definitions and/or waiver setup file as needed, and re-run the Calibre PERC LDL flow until all waivers are correctly
Figure 2 demonstrates the typical waiver generation and usage flow for Calibre PERC-LDL P2P/CD/DRC verification.
Calibre PERC reliability rule checking runs the same way and generates the same set of results, regardless of whether or not a waiver flow is enabled. The only difference is the categorization of the results. If the waiver flow is disabled, then all results are output to the report file as violations. If the waiver flow is enabled, the Calibre PERC process first applies the defined waivers to the results, which transforms the original results into a new (potentially smaller) set of non-waived results and a set of waived results, according to the outcome of the waiver analysis. The Calibre PERC process then outputs the new sets to the report file as violations and waived results.
Once the waiver flow is established and verified, engineers can safely disregard the check results in the waivers results database, saving the time and resources that would have otherwise been spent debugging these error results.
Automated waiver processing has been a part of design verification flows for some time, saving design teams significant time in their schedules by allowing them to disregard error results that are known to be insignificant or irrelevant to manufacturing success.
However, reliability rule checks introduce unique processing complexities with their need to combine topological and geometrical information. While waivers can be an important part of an efficient reliability verification flow, they must be applied and processed accurately to ensure the integrity of the design is maintained. Waiver processing for reliability checks must incorporate the same unique LDL processing used for routine reliability verification runs to ensure waivers are correctly identified and applied.
Automated solutions that can process waivers for LDL DRC, P2P parasitic resistance, and CD checks accurately and efficiently are available. Design teams looking to shave time from their delivery schedules should consider adopting a reliability check waivers process to minimize the time spent in debugging and maximize the effectiveness of their reliability verification flow.
 James Paris, “Physical IP Waiver Management with Calibre Auto-Waivers,” Mentor, a Siemens Business. May, 2016.
 “Calibre Auto-Waivers,” Mentor, a Siemens Business.
 “Full-Chip Electrical Reliability Verification: A New Approach for Advanced Nodes,” Mentor, a Siemens Business. Oct., 2017.
 P. Gibson, Z. Lu, F. Pikus, S. Srinivasan, “A Framework for Logic-Aware Layout Analysis,” 2010 11th International Symposium on Quality Electronic Design (ISQED), San Jose, CA, 2010, pp. 171-175. https://ieeexplore.ieee.org/ document/5450415
 Dina Medhat, “Automated waiver management for IC reliability verification,” Mentor, a Siemens Business, July 2018.