Cadence Design Systems

Bob Smith of the ESD Alliance describes how we can promote the ongoing evolution of the design ecosystem.

Portable stimulus and formal verification provide the means to handle the challenge of verifying cache-coherent SoC interconnects.

Emulators have come a long way since their first introduction nearly three decades ago.

In both data centers and automobiles deep learning is taking hold. But it is a technique that challenges conventional microprocessors, leading system designers to look at alternative architectures for acceleration.

What can you add to a challenging project without pushing out deadlines and muddling communication?

2016 marks the 20th anniversary of the term Electronic System Level (ESL), introduced by Gary Smith in 1996. Where are we now? And how will developments this year push the frontiers of practical ESL design?

The 10nm process node calls for the use of SOCV techniques during timing signoff to avoid leaving too much performance on the table.

The arrival of USB Type C provides an opportunity for SoC design teams with opportunities to provide customers with significant cost savings. Integrated IP will help the process.

The arrival of the 10nm process will impact the way that designers approach custom and mixed-signal layout. Cadence Design Systems has made changes to its Virtuoso environment that deploy increased automation support and electrically-aware layout to deal with the upcoming issues.

The 10nm process will see changes to multiple patterning that demands changes in the implementation flow, along with an increased focus on the effects of variability.