DVFS

April 29, 2021

DVCon Europe best paper assesses clock design

The best paper at DVCon Europe 2020 analyzed different multiclock strategies for SoCs for their power and flexibility
Expert Insight  |  Topics: EDA - IC Implementation  |  Tags: , , , ,   |  Organizations:
July 13, 2014
ST/CEA-Leti 'Frisbee' wide-voltage DSP

DVFS and body bias

Dynamic voltage and frequency scaling is effective for low-power VLSI design. Body or back bias can provide additional control over leakage and performance.
Guide  |  Topics: EDA - IC Implementation  |  Tags: , , , ,

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