Effective formal verification demands striking a careful balance in the use of constraints – too many slows things down, but too few may let bugs slip through.
Andy Ladd highlights the wide range of peak-power concerns around plugged-in devices.
An introduction to how virtual emulation has fueled the application of co-modeling for complex design verification.
Ashish Darbari describes a formal technique that fuels a rapid, predictable and highly effective methodology.
Lauro Rizzatti gets a reality check on AI for both design tools and designs themselves from the formal verification specialist.
Artificial intelligence and machine learning require the performance and flexibility offered by embedded FPGA (eFPGA) technology.
Insights from research into reliability at Imec led to self-learning chips, security technologies, and finFET biosensors.
Ashish Darbari sets out the fundamental qualities of a successful formal verification project.
In an exclusive interview, Lauro Rizzatti discusses the increasing verification challenges for drone SoCs with Bo Shen, founder of fabless specialist Artosyn.
Still using custom layout or place and route tools here? Ditch that time-consuming practice for a real database merge flow.
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