IJTAG: delivering an industry platform for IP test and integration
Mentor's Stephen Pateras explains how the proposed IJTAG standard speeds IP test by replacing time-consuming custom and ad hoc methodologies.
Verification
Synopsys FPGA prototyping launch puts pragmatism first
HAPS-70 boards launch with latest Xilinx chips, high-speed time-domain multiplexing and Synopsys' take on the debug crunch.
Tektronix aims to slash FPGA prototype debug time
Second generation Certus tool seeks to deliver RTL-level visibility on FPGA boards via a huge boost in signals you can instrument for debug.
Mentor Graphics CEO Wally Rhines – Interview
The Mentor chief discusses ESL-based low power, emulation, 32nm to 20nm and using tools in the cloud.
‘Known unknowns’ and the Cadence take on verification IP
Reviewing some of the sector's main trends with Susan Peterson, group director for VIP at the market leader.
Using verification IP to master AMBA and wider protocol proliferation
How and why Huawei's Hisilicon and DSP specialist CEVA tapped Cadence to implement ARM protocols.
Mentor extends Questa with formal coverage checks
New features provide enhanced formal checking analysis, code coverage closure and extended clock domain crossing analysis.
Synopsys buys EVE and the death of dogma
The EDA giant fills out its prototyping and verification line-up with a long-mooted acquisition, and is set to become the first of the 'big three' to offer an in-house soup-to-nuts flow.
Verification challenges require surgical precision
The verification challenge is best addressed by a combination of highly targeted tools, according to Pranav Ashar, CTO of Real Intent.
Aart de Geus on the changing face of EDA
The president and co-CEO of Synopsys provides his take on the mounting influence of software and physical effects in the creation of SoCs.
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