DVCon Europe returns to live format
DVCon Europe will be held as a live event in Munich in early December.
Blog Topics
Go inside proposals for common chiplet models
Chiplets will need models to guarantee heterogenous SiP implementation. A cross-industry working group describes its progress so far.
Verifying the new namespace storage options in NVMe 2.0
The NVMe 2.0 specification has introduced two namespace options that boost SSD performance while optimizing storage life.
Nvidia open to chiplet standards
Nvidia says it will support the UCIe chiplet interface standard once it has "stabilized" while opening up its latest form of NVLink to other companies.
Learn strategies for better measurement and test in simulation-based PCB design
A new white paper offers useful tips and techniques for PDN analysis and performance optimization in designs such as those using DDR4.
Verification engineers look to better skills to beat schedules
A panel at DVCon argued too much of a focus on point tools coupled with challenges with interoperability and cross-industry cooperation is hindering the ability of SoC teams to design and verify complex products.
Synopsys talks AI in verification at DVCon
Synopsys R&D vice president Manish Pandey described the ways in which the tools supplier has harnessed machine learning so far to gain speedups and improvements in coverage.
Arm aims for IPO as Nvidia calls off its bid
Nvidia has decided to give up on acquiring Arm from SoftBank. The IP provider will now aim for an IPO by the end of March 2023.
How digital twin evaluations optimize STCO-based design
System Technology Co-optimization raises various SI, PI, thermal, mechanical and warp risks due to its use of advanced packaging. Early-stage prototyping mitigates them.
Choose the right advanced packaging methodology for metal fill rules
Advanced packaging requirements from foundries and OSATs pose stringent challenges. A new paper describes three ways of satisfying them.