Blog Topics

Imperas has put together a suite of tools to verify that custom RISC-V processor cores remain compatible with the common infrastructure behind the open-source instruction set.

Breker will highlight its latest work on stress-testing processor, storage and I/O architectures during DAC 2021 this week.

The formal specialist is offering courses across six tiers, including case studies and lab work, with immediate availability.

The design and verification IP specialist will present its full range, including the Smart Compiler, at next week's Design Automation Conference.

DAC 2021 is looming and here is our first round up of a major EDA player's plans for the physical event in San Francisco.

A new white paper examines how to develop architectures around the main E/E elements placing growing demands on automotive engineering teams.

University of Florida researcher proposes third-party checks on chiplets to demonstrate they are free of trojans.

A £6.5m grant will fund the development of memories and other IP to improve the control of qubits in quantum computers.

Cloud computing is gaining ground in EDA but close to a third of organizations are planning to stay with on-premises computing for the foreseeable future, according to a survey commissioned by IC Manage.

Sondrel has combined EDA tools with custom SystemC and Python code to develop a system that can help automate the detailed performance analysis of high-level architectures before RTL is generated.