Blog Topics

May 21, 2013

Automotive benchmark puts focus on power consumption

Vehicle-maker Volkswagen is putting its weight behind a set of microcontroller benchmarks that focus on energy consumption rather than performance.
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May 21, 2013

Aldec automates safety-critical traceability

Spec-TRACER addresses stringent design reporting demands in safety-critical markets, some of which are moving into the mainstream.
May 21, 2013

DAC 2013: The Gary Smith EDA ‘what to see’ list is live

Whether your going to DAC 2013 or not, the EDA analyst's round-up is an invaluable guide to design trends and the tool vendors most actively addressing them.
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May 20, 2013

Cadence tackles timing signoff with Tempus

Cadence Design Systems has launched a timing-signoff tool that uses parallel processing and place-and-route algorithms to try to speed up time to tapeout.
May 20, 2013

TVS expands VIP library

Test and Verification Solutions has expanded its library of verification IP to cover protocols in MIPI, memories, serial IO and communication.
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May 15, 2013

SureCore picks up grant for low-power, nanometer SRAM IP

Physical-IP startup SureCore has been awarded $380,000 to build a demo chip for a low-power SRAM design the company is aiming at finFET and FD-SOI processes.
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May 14, 2013

Altera buys into power management with Enpirion

Altera has bought fabless power-management specialist Enpirion in an expansion intended to support its core business of FPGAs.
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May 14, 2013

Real Intent-DeFacTo sign-off flow for RTL combines CDC and DFT

Real Intent and DeFacTo Technologies combine clock-domain crossing and design for test tools in RTL sign-off flow.
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May 14, 2013

Jasper adds low-power App to formal family

Jasper Design Automation's modular concept moves into a hot area in SoC design to verify specs are still met after power management circuitry is inserted.
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May 14, 2013

Forte Cynthesizer aims at performance, power and ease of use

The fifth generation of Forte Design System's Cynthesizer tool is a slice of system-level evangelism.
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