Blog Topics

Altera has bought fabless power-management specialist Enpirion in an expansion intended to support its core business of FPGAs.

Real Intent and DeFacTo Technologies combine clock-domain crossing and design for test tools in RTL sign-off flow.

Jasper Design Automation's modular concept moves into a hot area in SoC design to verify specs are still met after power management circuitry is inserted.

The fifth generation of Forte Design System's Cynthesizer tool is a slice of system-level evangelism.

But you can still get in for free by registering for the 'I Love DAC' scheme by this Friday (May 17th).

Leaders from Cadence, Jasper, Mentor and Synopsys are late additions to DAC 2013, giving 15-minute pre-keynote talks previewing design's next half century.

ARM could see shipments of embedded processors based on its architecture begin to outpace its rump market in mobile within four years if growth continues at current levels.

Cadence Design Systems has decided to embrace IEEE 1801, derived from the Unified Power Format (UPF), providing support alongside the Common Power Format (CPF).

Cadence Design Systems has decided to buy Poland-based IP developer Evatronix as part of a plan to round out its portfolio of interfaces for SoC designs.

Cadence-and-Synopsys co-founder and Freescale's new CEO join the DAC 2013 program, while Qualcomm and TI line up to discuss their work in mobile comms as well as taking your questions.