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Cadence Design Systems has rolled out a new version of Virtuoso that deals with the physical-implementation issues that arise in the sub-28nm nodes.

Xilinx aims to be first of the FPGA makers to produce 20nm devices, expecting to move to production samples for some products by the end of the year.

To get others to adopt its GPU cores, Nvidia must quickly build partnerships with tool vendors and foundries that guarantee easy implementation.

Graphics chipmaker nVidia has said it plans to license as IP cores some of its technology in the hope of building up a customer base among other chipmakers and systems houses developing their own SoCs.

Design security is a major target for Microsemi’s update to its Igloo series of flash memory-based FPGAs, which add an ARM-oriented memory subsystem.

SystemVerilog and Synopsys Verdi integration are among further enhancements as clock domain crossing competition intensifies.

Atmel has launched its first family of microcontrollers based on ARM's Cortex M0+ with features to ease PCB design and provide programmable serial ports.

Latest addition to DesignWare portfolio balances trade-offs across CPUs, GPUs and DSPs while automating custom design techniques such as multi-bit flip flops.

Altera has disclosed a number of the features that will make it into the top end of its upcoming 'Generation 10' family of FPGAs.

The arrival of the finFET brings with it simulation and physical restrictions that might lead teams to resort to layout automation to get the job done.