Blog Topics

The increasing use of graphics in mobile SoCs means that finFET processes need to be optimised for density and power - as well as early availability at low risk.

Deal creates methodologies and tools to help deliver IP and SoC assemblies verified using formal methods. Low-power verification strategy also launched.

The effort needed in timing signoff could lead to a shift in design towards asynchronous techniques unless advanced OCV technologies improve.

CMOS approaches are likely to underpin electronics for the next century, according to Chenming Hu, father of the finFET

The group that developed the IEEE 1801 Unified Power Format standard is looking to bringing power modeling and estimation to the system level for version 3.0, due in 2015.

The EDA industry has a way to capture the embedded software market, analyst Gary Smith said ahead of DAC. But it’s not through tools – it’s through models.

The latest revision of the IEEE 1801 Unified Power Format standard for verifying low-power designs has been made available through the IEEE Get Program.

Xilinx and TSMC are forming a single engineering team to accelerate development of a family of finFET-based field programmable gate arrays (FPGAs).

Fabless designers and IP providers need process simulation tools to understand how process variability could affect their designs.

A look at what you can learn about design for manufacturability and yield at this year's Design Automation Conference