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Wire harness margins are tight yet quotes still need to be turned on a dime. Integrating that process into existing tools aims to help.

Plan around 193nm immersion lithography. Alternatives are years off and not guaranteed, says analyst group

Sessions at the DAC 2013 conference in Austin, Texas focus on low-power design and engineering low-energy systems from the system level down to physical.

DAC 2013's technical program has four sessions on innovation for verification. Some of the hot topics being covered include 3DIC and analog.

Vehicle-maker Volkswagen is putting its weight behind a set of microcontroller benchmarks that focus on energy consumption rather than performance.

Spec-TRACER addresses stringent design reporting demands in safety-critical markets, some of which are moving into the mainstream.

Whether your going to DAC 2013 or not, the EDA analyst's round-up is an invaluable guide to design trends and the tool vendors most actively addressing them.

Cadence Design Systems has launched a timing-signoff tool that uses parallel processing and place-and-route algorithms to try to speed up time to tapeout.

Test and Verification Solutions has expanded its library of verification IP to cover protocols in MIPI, memories, serial IO and communication.

Physical-IP startup SureCore has been awarded $380,000 to build a demo chip for a low-power SRAM design the company is aiming at finFET and FD-SOI processes.