Blog Topics

Real-value modelling and flows using the Open Access database will be among the focus topics of Cadence's Mixed-Signal Technology Summit on 10 October.

Design services company eSilicon has made freely available a tool it developed to streamline ordering for multi-project wafer (MPW) ‘shuttle’ services.

Research group CEA-Leti expects to have design kits ready for a 10nm FD-SOI process in June 2014

Accellera has vendor extensions for IP-XACT that allow tool-specific metadata to be added to support activities such as power-aware verification and floorplanning.

For the new web TV program Unhinged, Brian Fuller talked to venture capitalist Jim Hogan about the future of mixed-signal and the past of EDA.

RS Components is now offering a solid-modelling tool to work with its free PCB design tool to provide easier access to 3D mechanical design.

Synopsys user meet in Austin carries forward themes from Boston event.

In a keynote at the Intel Developer Forum, CEO Brian Krzanich said the company would start making 14nm processors by the year end and confirmed intel would license SoC designs to be fabbed by other companies.

Cadence Design Systems has upgraded its Palladium emulators to a maximum capacity of 2.3 billion gates and 50 per cent higher performance.

Synopsys automates standards-based hierarchical test insertion and improves test compression for SoCs; Mentor teams with ScanWorks for system-wide IJTAG.