EDA

May 5, 2013

Synopsys users gather for European SNUG meetings

Synopsys users will be gathering at a series of SNUG meetings across Europe over the next month to share insights and experience of using Synopsys tools
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May 5, 2013

IEDM2013 call for papers closing soon

It's time to act if you want your semiconductor device or process research to be considered for presentation at IEDM 2013 in Washington DC this December.
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April 29, 2013

DAC 2013 Preview IV: Management and Training Days

DAC 2013 will offer a series of dedicated training courses in SystemVerilog, SystemC, and ARM-based design as well as its regular management day bridging the gap between technology and business.
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April 29, 2013

CDNLive EMEA looms

CDNLive EMEA opens 6 May, providing delegates with an opportunity to find out what their peers are doing with Cadence Design Systems’ tools in real projects.
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April 25, 2013

Hear Alexander Graham Bell speak for the first time

And then bear in mind that the father of telephony is telling all design engineers a cautionary tale: Documentation. Documentation. Documentation.
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April 24, 2013

DAC 2013 Preview III: Embedded

DAC 2013 wants to bridge the gap between hardware and embedded software technical conferences, and has dedicated 35% of this year's technical program to that goal.
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April 18, 2013

Accellera publishes tag standard for soft IP

Accellera Systems Initiative has published version of 1.0 of its Soft IP Tagging standard for adding licensing information to RTL and other design files.
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April 18, 2013

ARM intros single-use licence for Big-Little

ARM has decided to put together a package deal for some of the components that will let prospective customers implement a multiprocessor subsystem in a single SoC design
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April 10, 2013

FinFET father headlines Mentor’s west coast user conference

Dr Chenming Hu joins Mentor CEO Wally Rhines and Xilinx SVP Victor Peng to keynote free day-long User2User in San Jose on April 25th, capping a full technical program.
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April 10, 2013

The wrong units of compute

Scale-out computing has demands so different from conventional applications that it could reshape the way to design one class of multicore processors.

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