How cloud computing is now delivering efficiencies for IC design
A Mentor-Microsoft-AMD pathfinder demonstrates the potential benefits of cloud-based physical verification.
Siemens EDA
Keep chip designs on the level with CMP simulation and dummy fill optimization
This case study shows how rising CMP simulation quality can be leveraged to detect the position and type of planarity hotspots before manufacture and verify the planarity of a layout.
Delivering on security for Linux-based medical devices
How should you address the monitoring and resource challenges in maintaining security for Linux devices.
How to gain a competitive edge with advanced DFT
Learn how the latest design for test innovations deliver efficiency and profitability across the design flow.
How to achieve accurate reset domain crossing verification
The authors describe an emerging methodology based on a hierarchical data model approach that satisfies the key requirements for RDC verification.
How automated power/ground short checks slash time during implementation
Early detection using design integrity checks during implementation from abstract LEF/DEF inputs can deliver major efficiencies.
Automate P2P resistance checking for better, faster ESD protection
ESD has always been a major issue but with increasing densities and growing die sizes it is becoming a higher order concern. Automation and vizualization can help manage the task.
How MaxLinear got faster signoff DRC while optimizing reliability and manufacturability
The RF and AMS specialist turned to design software that allowed it to run design checks during place and route.
Make it easier to exercise state machines with SystemVerilog
How the use of declarative, constraint-based descriptions can help you focus command sequences on areas of interest.
A better way to debug P2P results
P2P (point-to-point) resistance is fundamental to IC reliability verification. Handle it more efficiently with detailed, automated path layout analysis.