Executable specifications boost SoC and IP efficiency
Automating executable specifications as they evolve can deliver major efficiencies.
IP
Machine learning overcomes library challenges at the latest process nodes
From 16nm, new complexities hinder .lib file characterization and verification but machine learning now offers an efficient way of managing them.
How to achieve accurate reset domain crossing verification
The authors describe an emerging methodology based on a hierarchical data model approach that satisfies the key requirements for RDC verification.
High-level synthesis for AI: Part Two
How Chips&Media used HLS on the development of a computer vision IP block.
DVCon China launches this April in Shanghai
DVCon China general chair Andy Liu discusses Accellera’s new addition to its design and verification conference series (简体中文).
How new RTL floorplanning techniques speed physical design
Advances in RTL floorplanning help cut front-to-back-end iterations, speed synthesis by 10X and boast the capacity needed for today's designs.
Mixed-signal verification of advanced SoCs using VCS AMS
How ST Microelectronics uses Synopsys' VCS AMS, combining VCS functional verification and CustomSim, to verify one of its mixed-signal designs
Keeping high-speed designs clean with ERC
Electrical rule checks (ERC) are now available to deal with increasing PCB design complexity, speed project delivery and protect the intellectual property within them.
IP-to-SoC prototyping demands consistency
Many problems arise during the IP-to-SoC phase of FPGA-based prototyping due to the mix-and-match nature of the prototypes not the actual designs.
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