How emulation’s virtual mode boosts productivity: Part One
This two-part article describes advantages when using a hardware emulation platform in virtual mode compared with in-circuit-emulation.
Siemens EDA
Focus your use of Portable Stimulus on three key axes
Portable Stimulus allows reuse along horizontal, vertical and technique axes, but you need to be aware of the strengths and weaknesses of each to get the greatest benefits.
How critical area analysis improves yield
CAA is a valuable tool available to both design engineers and foundries to help them avoid layout-dependent effects during manufacturing.
High-level synthesis for AI: Part Two
How Chips&Media used HLS on the development of a computer vision IP block.
High-level synthesis for AI: Part One
The computational and algorithmic demands made by computer vision systems highlight HLS' value for AI system development.
Use evolving DRC to automate high-voltage and multi-power domain verification
Automated voltage-aware DRC addresses the reliability verification challenges in today’s high-voltage and multiple power domain applications.
Enabling the move to a system-centric view
Bob Smith of the ESD Alliance describes how we can promote the ongoing evolution of the design ecosystem.
Validating on-chip variation: Is your library’s LVF data correct?
Machine learning techniques help ensure the validity of Liberty Variation Format information for OCV analysis at lower process nodes.
Practical mixed-signal defect and fault injection automation and simulation
This defect and fault injection primer looks at how to standardize definitions, decide injection volume, measure activity, manage simulation, optimize test time and more.
Fast, accurate layout merging for SoC flows
How to achieve efficient merging of data from formats such as OASIS, GDS, and OpenAccess to ensure timely verification through DRC runs.
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