Use machine learning and visualization to accelerate Liberty file verification
Learn how to bring together your NLDM and CCS models to reach timing closure faster with Solido Analytics.
Siemens EDA
Out-of-sync data issues in parallel design flows need automated design integrity checks
Overcome problems created by mismatches between library exchange format (LEF) and GDS or OASIS representations to avoid design delays.
How you can decide what level of DRC you need when you need it
Using on-demand rule checks during place-and-route boosts efficiency and design quality.
May the Cloud be with you
How to unify your design team to defeat the dark side of board systems design.
How automated static checks help verify complex circuits for better performance and reliability
Learn how power-intent, LDEs, ESD and voltage-aware spacing techniques can particularly benefit from the use of static verification checks.
Spiral in on silicon bugs in six formal steps
The best paper winner at DVCon 2021 details a comprehensive methodology for making the best use of formal verification for bug hunting
The path to full functional monitoring
Joe Sawicki of Siemens EDA recently addressed the main trends in design delivery from architecture to validation to digital twins - and where they may soon take the industry and its products.
Silicon lifecycle solutions help you listen to your chip
SLS brings the power of product lifecycle management to the increasingly complex oversight challenges in electronic systems design.
Streaming Scan Network technology delivers ‘no compromise’ DFT for AI designs
A new technique is especially efficient for AI chips with modular, tiled design strategies leveraging multiple instantiations of the same cores.
Machine learning overcomes library challenges at the latest process nodes
From 16nm, new complexities hinder .lib file characterization and verification but machine learning now offers an efficient way of managing them.
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