analog

Symmetry verification for analog and custom IC needs to evolve beyond current time-consuming and hard-to-use techniques.

Because of the high analog content in memory designs, designers must understand how various effects impact reliability and performance.

PIM memory boosts efficiency by operating on data without moving it to the CPU but realizing this type of novel technology posed power integration and planning challenges.

The RF and AMS specialist turned to design software that allowed it to run design checks during place and route.

This defect and fault injection primer looks at how to standardize definitions, decide injection volume, measure activity, manage simulation, optimize test time and more.

In-design DRC is a technique that frees up engineers from many of the challenges of delivering AMS design under ever more complex design rules.

DVCon China general chair Andy Liu discusses Accellera’s new addition to its design and verification conference series (简体中文).

DVCon中国大会主席刘红亮讨论了Accellera新增的DVCon中国ASIC设计和验证会议的看点。

Traditional techniques are being challenged by shortening design cycles and the effects of later process nodes.

Although FastSPICE simulators are in almost every design flow, requirements are moving beyond the capabilities they can provide. Parallel processing provides a solution.