CDC sequential reconvergence can be systematically verified without exhaustive manual review by using the circuit model in this methodology.
CDC-related metastability is hard to catch by hand and processes are error prone. Tools offer a more comprehensive approach.
The authors describe an emerging methodology based on a hierarchical data model approach that satisfies the key requirements for RDC verification.
A new clock-domain crossing methodology is described and results provided to show how automation delivers greater efficiency.
Escape formal's narrower definitions with a flow that shows you how to Avoid, Detect, Erase, Prove Absence and Tape Out while avoiding bugs.
Complex processes and aggressive synthesis interventions are increasing the risks of metastability, creating a need for netlist-level CDC verification
A look at three techniques to verify the validity of signals moving between clock domains
CDC violations are now so complex that it takes a combined block and full SoC level verification strategy to catch and fix all the bugs
Formal techniques can be applied to various parts of the verification challenge, including low-power and clock domain-crossing issues
The argument for an integrated approach to SoC verification
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