The authors describe an emerging methodology based on a hierarchical data model approach that satisfies the key requirements for RDC verification.
A new clock-domain crossing methodology is described and results provided to show how automation delivers greater efficiency.
Escape formal's narrower definitions with a flow that shows you how to Avoid, Detect, Erase, Prove Absence and Tape Out while avoiding bugs.
Complex processes and aggressive synthesis interventions are increasing the risks of metastability, creating a need for netlist-level CDC verification
A look at three techniques to verify the validity of signals moving between clock domains
CDC violations are now so complex that it takes a combined block and full SoC level verification strategy to catch and fix all the bugs
Formal techniques can be applied to various parts of the verification challenge, including low-power and clock domain-crossing issues
The argument for an integrated approach to SoC verification
How Wall Street's vastly resourced IT teams already point the way to cheaper, faster and more efficient verification by putting goals not tools first.
As designs get larger and stress the ability of simulation to exercise an SoC, formal techniques have become essential parts of design and verification.
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