Fast, accurate layout merging for SoC flows
How to achieve efficient merging of data from formats such as OASIS, GDS, and OpenAccess to ensure timely verification through DRC runs.
Siemens EDA
Emulation for AI: Part Two
The second part of this feature looks at how Wave Computing's objectives with its dataflow processing unit for AI mapped to the use of emulation in its development.
Emulation for AI: Part One
An increasing number of AI players are building their own silicon and finding that emulation is key to overcoming the major challenges.
A better way to manage error reporting at the chip and block levels
In a continuous-build design flow, at which level should your error markers be addressed?
Create more flexible virtual sequences with Portable Stimulus
Virtual sequences are considered challenging to write and re-use. Learn how to overcome those issues with the new Portable Stimulus Standard in this DMA-based case study.
Enhanced model-based hinting may be the edge you need below 20nm
A detailed dive into how MBH strategies for litho hotspots have been enhanced to deal with double patterning at 20nm and below.
Win on the fault campaign trail with formal
How formal verification for the ISO26262 automotive functional safety delivers the full activation, propagation, and observation in the form of proven and exhaustive results.
Adding system-level, post-layout electrical analysis to HDAP design and verification
Adoption of high-density advanced packaging (HDAP) needs tools and supports to build designers' confidence in the emerging technology.
Reliability verification: It’s all about the baseline
How you can use the dedicated rule decks now being provided by foundries as the foundation for a reliability verification flow.
How to improve throughput for gate-level simulation
Innovative methodologies, strategies and tool features help overcome other inefficiencies in complex but necessary simulations.
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