Siemens EDA

March 9, 2018
Saunder Peng is a Senior Application Engineer with Mentor, a Siemens Business. He received his B.S degree in Electrical Engineering from the University of California at Los Angeles, and his M.S. in Electrical Engineering from Columbia University, New York.

A better way to merge design files for physical verification

Still using custom layout or place and route tools here? Ditch that time-consuming practice for a real database merge flow.
February 28, 2018

How to achieve more accurate NAND soft-bit error injection

The article describes a pre-silicon strategy for the design and verification of SSD controllers that is faster and more flexible than ICE using physical NAND on a daughter-card.
Article  |  Topics: EDA Topics, EDA - Verification  |  Tags: , , ,   |  Organizations:
February 1, 2018
Design space exploration feature

Design space exploration finds hotspots during early process development

A new technique has been developed to catch potential new lithography issues when little design data is available for incoming nodes.
January 15, 2018
Physical Verification Efficiencies - featured image

Three ways to lift productivity during physical verification

How to get the best PV results by reducing computational demands; handling data more efficiently and exploiting parallelization.
Article  |  Topics: EDA - DFM, Verification  |  Tags: , , , ,   |  Organizations:
December 22, 2017

Improve custom/AMS design and productivity with in-design DRC

In-design DRC is a technique that frees up engineers from many of the challenges of delivering AMS design under ever more complex design rules.
Article  |  Topics: EDA - IC Implementation  |  Tags: , , , , , ,   |  Organizations:
December 4, 2017
Richard Pugh featured image SSD expert insight

Data-hungry applications demand emulation

Richard Pugh shows how the fast-growing market for drone silicon highlights emulation's power where high data volumes are critical.
Expert Insight  |  Topics: EDA - Verification  |  Tags: , , , , , , ,   |  Organizations:
November 24, 2017
John Ferguson is the Director of Marketing for Calibre DRC Applications at Mentor, a Siemens Business, in Wilsonville, Oregon, with extensive experience in physical design verification. He holds a BS degree in Physics from McGill University, an MS in Applied Physics from the University of Massachusetts, and a PhD in Electrical Engineering from the Oregon Graduate Institute of Science and Technology.

Assessing the true cost of node transitions

John Ferguson reviews the key capital metrics you need to review when deciding whether to move to a new process.
October 30, 2017
Debug case study for ARM/AXI based design

Case study: Verifying and optimizing software for power on SoCs

How emulation was used to debug out-of-spec power on a multicore ARM design using the AXI bus.
October 27, 2017
Featured image - double patterning at advanced nodes

Catch multi-patterning errors clearly at advanced nodes

How to address increasingly complex patterning issues and debug them efficiently as design moves toward 12 and 10nm.
Article  |  Topics: EDA - DFM, - EDA Topics, EDA - Verification  |  Tags: , , , , , ,   |  Organizations:
October 18, 2017
Channel Operating Margin featured image

How Channel Operating Margin helps Gigabit Ethernet PCB analysis

The COM methodology is being extended and more widely adopted across high-speed designs thanks to deeper tool integration.
Article  |  Topics: PCB - Design Integrity, - PCB Topics  |  Tags: , , , , , , , ,   |  Organizations: ,

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