ARM

September 9, 2019

Getting better results faster with a unified RTL-to-GDSII product

Complex SoCs need systemic optimisation to achieve best time to results, enabled by the use of a unified RTL-to-GDSII flow underpinned by a unified data model.
Article  |  Topics: EDA - IC Implementation  |  Tags: , , ,   |  Organizations: ,
August 15, 2019
Ron Press is the technology enablement director of the Tessent product family at Mentor, A Siemens Business. He is a member of the International Test Conference (ITC) Steering Committee, a Golden Core member of the IEEE Computer Society, and a Senior Member of the IEEE.

Achieving more efficient hierarchical DFT for Arm subsystems

Hierarchical DFT for Arm-based SoCs is easier than ever with the arrival of a complete reference flow from Mentor and Arm.
Expert Insight  |  Topics: EDA - DFT, - EDA Topics  |  Tags: ,   |  Organizations: ,
April 9, 2018

Keeping up with the bandwidth demands of embedded displays

Increasing resolutions and rising frame rates are making it more challenging than ever to drive embedded displays effectively.
Article  |  Topics: Embedded - Architecture & Design, IP - Selection  |  Tags: , , , ,   |  Organizations: , ,
March 1, 2018

Driving 4K smartphone and AR/VR device displays

How to combine a display processing unit from one company and a MIPI Display Serial Interface solution from another to build 4K embedded displays for smartphones and AR/VR devices.
Article  |  Topics: Embedded - Architecture & Design, IP - Selection  |  Tags: , , , ,   |  Organizations: , , ,
October 30, 2017
Debug case study for ARM/AXI based design

Case study: Verifying and optimizing software for power on SoCs

How emulation was used to debug out-of-spec power on a multicore ARM design using the AXI bus.
May 22, 2017
Ashish Darbari is CEO of formal verification consultancy Axiomise.

Introducing Doc Formal: the journey so far

Our new columnist introduces himself and traces the progress of formal verification over the last two decades. Join the discussion.
November 2, 2015

How to cut verification time with VIP

This article shows practical ways to use verification IP for greater productivity with specific code examples from Mentor Graphics' Questa platform.
Article  |  Topics: EDA - Verification  |  Tags: , , , ,   |  Organizations: ,
July 20, 2015
TSMC finFET

Lessons learned in the finFET trenches

In sessions at the 2015 Design Automation Conference, engineers who had worked on finFET-oriented projects revealed how the technology has changed their design practices and where others may want to think twice about making the move.
May 15, 2015
Four-core Cortex-A72 layout example

Cortex-A72: microarchitecture tweaks focus on efficiency

ARM has revealed a number of details of the microarchitecture that underpins its flagship Cortex-A72 as the processor moves towards its production release.
May 6, 2015

Fixing late ECOs in ARM core subsystems at STMicroelectronics

Using equivalence checking to validate ECOs in ARM core subsystem development at STMicroelectronics

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