Fast emerging options, like RISC-V, could foster massive growth in design but verification still needs commercial tools, a Semicon West panel found.
Learn how the latest design for test innovations deliver efficiency and profitability across the design flow.
Complex SoCs need systemic optimisation to achieve best time to results, enabled by the use of a unified RTL-to-GDSII flow underpinned by a unified data model.
Hierarchical DFT for Arm-based SoCs is easier than ever with the arrival of a complete reference flow from Mentor and Arm.
Increasing resolutions and rising frame rates are making it more challenging than ever to drive embedded displays effectively.
How to combine a display processing unit from one company and a MIPI Display Serial Interface solution from another to build 4K embedded displays for smartphones and AR/VR devices.
How emulation was used to debug out-of-spec power on a multicore ARM design using the AXI bus.
Our new columnist introduces himself and traces the progress of formal verification over the last two decades. Join the discussion.
This article shows practical ways to use verification IP for greater productivity with specific code examples from Mentor Graphics' Questa platform.
In sessions at the 2015 Design Automation Conference, engineers who had worked on finFET-oriented projects revealed how the technology has changed their design practices and where others may want to think twice about making the move.
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