Moving up to PCIe 5.0 speeds demands rethinking everything from silicon design through choice of PCB material and connectors up to track layout and validation.
The COM methodology is being extended and more widely adopted across high-speed designs thanks to deeper tool integration.
Reliability is growing to match security as a key challenge for PCB design. These tools and techniques will help you rise to it.
Ethernet is set to become one of the key communications standards for automotive. Early system-level simulation lets designers gauge performance before moving to hardware prototypes.
The introduction of the DDR4 memory-bus standard will allow system designers to meet aggressive performance targets for their next-generation systems. But the changes required to support the higher datarates of DDR4 place stringent demands on the PCB designer.
Soft blocking to prevent cell spreading and other placement-optimization techniques helped improve power and clock speed on a Cortex-M7 test chip designed by ARM and Cadence.
A panel session at DAC 2014 focused on the problems of high-speed, board-level interconnect and the roles of codesign and power integrity in solving them.
In a standing-room-only talk at the recent DesignCon conference, Eric Bogatin explained why comedian Henny Youngman could help them with signal integrity on PCBs.
The number of scenarios needed for MCMM timing analysis has skyrocketed. IC implementation calls for a concurrent approach to deal with the issue.
Electrical rule checks (ERC) are now available to deal with increasing PCB design complexity, speed project delivery and protect the intellectual property within them.
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