Assessing the true cost of node transitions
John Ferguson reviews the key capital metrics you need to review when deciding whether to move to a new process.
28nm
20nm
The 20nm node can offer power, performance and area advantages, but making these gains takes a deep understanding of the interactions between process and design.
Interconnect resistance
A number of effects have led to a dramatic increase in interconnect resistance in the sub-32nm process nodes that demands the use of smarter routing.
The requirements for complete RTL signoff
Problems become expensive to fix after the place-and-route stage so it's time to think seriously about the role of RTL signoff within the design flow.
Accelerating process migration in advanced ASIC design at Bull
How the HPC company used Synopsys' Lynx Design System to standardise its flow and simplify migration to the next node.
Improving SoC productivity through automatic design rule waiver processing for legacy IP
You can waive some physical verification errors related to legacy IP found in foundry DRC checks. Knowing which has involved lengthy manual analysis. TSMC is enhancing the process with automation.
The challenge of analog, mixed-signal and custom physical implementation at 28nm
The 28nm process node has once more raised the design bar in terms of the DFM checks needed to realize a design. This is particularly true for analog and mixed-signal engineering, where rules that could once be maintained manually now need to be addressed in a more integrated, automated, and timely way. The article explores [...]
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