Archives

Cadence Design Systems has launched a timing-signoff tool that uses parallel processing and place-and-route algorithms to try to speed up time to tapeout.

Test and Verification Solutions has expanded its library of verification IP to cover protocols in MIPI, memories, serial IO and communication.

Physical-IP startup SureCore has been awarded $380,000 to build a demo chip for a low-power SRAM design the company is aiming at finFET and FD-SOI processes.

Altera has bought fabless power-management specialist Enpirion in an expansion intended to support its core business of FPGAs.

Real Intent and DeFacTo Technologies combine clock-domain crossing and design for test tools in RTL sign-off flow.

Jasper Design Automation's modular concept moves into a hot area in SoC design to verify specs are still met after power management circuitry is inserted.

The fifth generation of Forte Design System's Cynthesizer tool is a slice of system-level evangelism.

But you can still get in for free by registering for the 'I Love DAC' scheme by this Friday (May 17th).

Leaders from Cadence, Jasper, Mentor and Synopsys are late additions to DAC 2013, giving 15-minute pre-keynote talks previewing design's next half century.

ARM could see shipments of embedded processors based on its architecture begin to outpace its rump market in mobile within four years if growth continues at current levels.