Safety and test IP heads for automotive AI applications
Automotive AI specialist FABU has licensed a portfolio of IP from Synopsys to help assemble ISO 26262-compliant SoCs
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Fast process access gets Moortec onto 7nm
Early access to tools for new processes is helping Moortec deliver IP to determine the real-time health of on-chip circuits.
Synopsys gets big-chip signoff boost from Innovium
Data-centre networking chip goes through full-chip design rule checking and layout-versus-schematic signoff on TSMC's 16nm finFET process in a day.
Video series details the physical verification process
Physical verification challenge of large SoCs on leading-edge processes detailed in video series
Ceva extends control-oriented DSP
Ceva has followed its IoT-oriented Ceva-X series of processor cores with a more powerful family that is designed to handle control and signal-processing algorithms using the same pipeline.
Closing code coverage with a hardware-aware HLS-to-RTL flow
Closing code coverage from HLS has been tricky because the C++ tools were built for software not hardware. But that is changing.
Synopsys announces DDR5 and LPDDR5 interface IP
Synopsys is targeting artificial intelligence (AI) and data centre SoCs as key application areas for the interface IP.
Microchip opts for RISC-V cores in SoC FPGA
Microsemi has put multiple RISC-V cores into a new generation of SoC FPGAs, intended for embedded systems that need to run Linux.
Leti takes the heat off monolithic 3D
CEA-Leti claimed at IEDM to have achieved major steps in bringing monolithic 3D integration closer to production readiness.
Achronix builds machine learning IP into eFPGA
Achronix has incorporated direct support for machine learning into the latest version of its eFPGA architecture.