Hosted by the Accellera Systems Initiative, DVCon Europe will follow a similar format to the US event on the 14 and 15 October 2014. The conference is looking for papers with a closing date of 8 April. One of the program vice chairs is Mike Bartley of UK-based Test & Verification Solutions, who has for several years run a series of verification-focused events around Europe.
As well as general verification topics, the conference is looking primarily for papers that look at:
- The application of system-level design and verification languages such as SystemC, SystemVerilog or e
- The use of SystemVerilog Assertions (SVA) or the Property Specification Language (PSL)
- Verification methodologies based on the Universal Verification Methodology (UVM)
- IP reuse, design automation and integration standards based on IP-XACT
- Low power design and verification using the Unified Power Format (UPF)