Refining DTCO to bridge data walls in system design
DTCO (design technology co-optimization) looks to address systemic verification challenges but the process still needs to be extended.
machine learning
Arm embraces Transformers with faster NPU
Arm has launched what the company claims is its highest-performance and most-efficient AI accelerator.
DVCon Europe calls for papers for 2024 event
DVCon Europe is looking for papers to be presented at this year’s event in mid-October.
DVCon gears up for March in San Jose
Workshops on portable stimulus, functional safety, verification of RISC-V processors, and design with chiplets and large language models will feature at the upcoming 2024 DVCon US.
Arm gives Helium to low-end Cortex-M core
Arm has added machine-learning extensions and pointer-security instructions to its latest Cortex-M series core.
Cadence combines ML techniques for power signoff
Cadence has linked several machine-learning approaches to build a tool that is designed to speed up the detection and diagnosis of on-chip power-integrity issues.
Imperas builds model of Tenstorrent AI core
Imperas Software has worked with AI specialist Tenstorrent to create and distribute a model of the Ascalon processor core.
HPC and AI provide keynote focus at DVCon Europe
DVCon Europe has announced its two keynote presentations, focusing on energy-efficient high-performance computing and machine learning.
AI’s possible roles in verification covered at VF2023
The recent Verification Futures Europe conference looked at what AI, from decision trees to foundation models, could do to speed up RTL checks.
Co-design underpins infrastructure acceleration at Google
At the recent VLSI Symposium, Google vice president Parthasarathy Ranganathan described the importance of co-design and the software stack in its data-center designs.
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