IP

Cadence Design Systems’ Tensilica division has launched a variant of its Vision P6 processor core to tackle embedded designs that need to run a mixture of imaging and deep learning-type algorithms.

PDK enables photonics prototyping on MPW runs and compatibility with volume production at STMicroelectronics at Crolles.

Xilinx plans to make reconfigurable computing the focus of its upcoming generation of FPGAs, which will be made on a 7nm finFET process at TSMC and expected to start sampling next year.

Accellera Systems Initiative has begun a project that may result in the creation of a standard to address security assurance for semiconductor IP cores.

Cadence and Imec have worked together on a project to tape out a test chip to explore manufacturing and design-rule options for the interconnect on future 3nm processes.

The Accellera Portable Stimulus Working Group has released for public review its current proposal for the verification standard it is working on.

Faster, lower power flash interface IP with built-in encryption/decryption speeds access to embedded and removable storage.

Ceva has decided to include neural network, vector processing and customized instruction sets in an IP platform for 5G NR terminals.

Arm plans to use its cryptography cores and technology from its Simulity Labs acquisition to SIM-based security into IoT devices.

Semiwise, a startup founded by University of Glasgow professor Asen Asenov and former CEO of Gold Standard Simulations (GSS), has developed a low-power CMOS transistor technology suitable for ultralow-power sensor nodes.