IP

Deal creates methodologies and tools to help deliver IP and SoC assemblies verified using formal methods. Low-power verification strategy also launched.

Fabless designers and IP providers need process simulation tools to understand how process variability could affect their designs.

Test and Verification Solutions has expanded its library of verification IP to cover protocols in MIPI, memories, serial IO and communication.

Physical-IP startup SureCore has been awarded $380,000 to build a demo chip for a low-power SRAM design the company is aiming at finFET and FD-SOI processes.

And then bear in mind that the father of telephony is telling all design engineers a cautionary tale: Documentation. Documentation. Documentation.

ARM has decided to put together a package deal for some of the components that will let prospective customers implement a multiprocessor subsystem in a single SoC design

Two vendors have announced early adopter software implementations of the new video compression standard that promises an up to 50% bandwidth cut against H.264.

An early shift to finFET processes is making developing IP libraries more challenging.

GlobalFoundries has signed deals to let the foundry offer power-saving clocks, a massively parallel floating-point processor and interface IP from Rambus. They are "uncommon solutions" to come from a foundry, the company claims.

MEMS relay-based devices offer the ultimate in subthreshold leakage: they don't have any. Design and technology advances are promising to overcome problems with reliability, design and speed, according to Tsu-Jae King Liu of UC Berkeley.