Blog Topics

Aldec updates tools to add support for the latest release of the VHDL verification methodology.

Study may point to new challenges in more bidirectional AMS implementations on SoC-class designs, though formal and emulation help keep respin count in check.

Benchmark study detects correlation between maturity of verification processes and the quality of designs when they reach production.

Use of the open-source RISC-V processor was tracked for the first time by the biennial study, finding notably high take-up.

Accellera Systems Initiative has published for open review version 2.0 of the Portable Test and Stimulus standard.

This year's IEDM will feature papers that exploit stacked nanoribbons to reduce CMOS footprint, graphene interconnects that support easier integration, and the variability prospects of 2D semiconductors.

Mentor's latest additions to Tessent aim to cut test time by a factor of four but remains tailored for increasing design complexity.

The Arm Cortex-A78C extends the reach of the core into larger tablets and brings in one of a series of memory-protections extensions that will be used in the company's standard cores.

The free-to-attend user meetings for Mentor clients will retain the same format mixing technical presentations with keynotes and networking.

Speakers at this year's DVCon Europe called on the hardware community to find inspiration in software-development trends.