Lessons learned in the finFET trenches

The first thing to consider when it comes to finFET design is to ask whether the migration is going to make economic sense. Afshin Montaz, engineering senior manager in Broadcom’s mixed-signal group, said in a panel organized by Cadence Design Systems on finFET design: “16nm is not for every product or every application. Compared to 28nm, the cost per transistor has actually gone up so you may not win [by moving]. The key advantage of 16nm is the speed. From the speed point of view, 16nm may make sense for you, or if you want to reduce power drastically [for the same performance]. But with those things in mind you have to be sure that it is the right place to be.”

Scott McCormack, director of SoC design, Freescale, added: “You don’t go into 16nm finFET to save money. It’s not for every part. It was power for us. There were market opportunities where we wanted to differentiate on power and find value that warranted the investment in 16nm finFET.

“The question is constantly changing. The cost is changing and we see a lot of improvement in finFET cost, but for Freescale the driving factor was power. But we are not going to put a small chip in there. The larger designs and power hungry designs are those that benefit.”

Jayonta Lahiri, vice president of engineering in ARM’s physical design group, said performance provides another driving force for finFETs: “There is a market demand for getting to the high performance point, providing higher frequency at a lower power envelope. ARM cores would never reach 3GHz in previous technologies. But now can in 16nm and at the right power point.”

Process spread

The shift in the cost equation is contributing to a spread in process usage at larger chipmakers, Montaz said: “We have a lot of different products with different requirements. We are actually designing at 40, 28, 20, and 16nm. It shows that every product needs a different process. FinFET gives you less power at faster speeds; the others stay at older nodes.”

McCormack said the Freescale team approached 16nm finFET design “with an abundance of caution”. He added: “But I don’t think that it was such a game-changer overall. We found the same problems as before but that a lot more attention to detail is required. Issues such as discrete [quantized] gate sizes, challenges of that nature really drove a lot of design iterations during closure. With Monte Carlo simulations there are a lot of static timing analysis corners to tackle. So we saw a lot of demand on compute resources. And there was a lot of DRC and LVS clean-up at the end because of the complexity of the design rules.

“We used an abundance of caution because of the costs involved. We learned a lot of those lessons at 28nm where we did a lot of chips in parallel. It looked like a lot of risk with 16nm so we picked one to focus on.

McCormack’s comments on focusing on one design were echoed at DAC by HiSilicon network processor business unit deputy general manager Yanqiu Daniel Diao, who pointed out that the company decided to skip two projects in order to focus on a key 16nm SoC.

Stage-based timing

Lahiri said the finFET process marked the point where stage-based static timing analysis became essential, which added to the compute burden. “But there was some easier stuff too. With the sizing of transistors, we quickly found out that for digital it can actually be easier compared to having arbitrary transistor widths. And the performance we could get was incredible for a given power envelope.”

Montaz said, despite the issues of fin quantization for analog design, the finFET has its advantages in terms of threshold-voltage matching, gain and better output impedance higher. “Transistor mismatch is lower and the on/off ratio is better.”

Montaz added: “There were a couple of difficult things that came about. There are a lot of new DRC rules that we didn’t have in 28nm, including double patterning and the fact that there is direction in metal routing. The vertical direction minimum width is different to the horizontal. So, putting a via in is more difficult. Even our senior layout people can’t remember all these rules. You really need real-time DRC EDA to be there to help you.

“The netlist has exploded because you have a lot of new elements that are unconnected, such as dummy transistors that you have to put in at the edge of a cell. Your via-0 contact to the first metal layer has been replaced by multilayer [MOL] interconnect. You have a lot more parasitic resistors, making simulation more difficult. So you need a better and faster EDA tool,” Montaz added. “Those are the two main challenges other than cost.”

Corner trimming

Some relaxation of the compute burden could be achieved by trimming the corners that need to be evaluated during timing closure. Double patterning has effectively doubled the number of corners. But some may turn out to have limited benefit compared to other more important combinations of mask shift, temperature and process effects.

McCormack said the risk of not performing a full evaluation currently outweigh the project-cost savings of corner optimization. “We haven’t gone through the exercise of reducing the number of corners. As the process matures we can start to move down that path.”

In a second Cadence panel focusing on implementation, TSMC deputy director Tom Quan said the emphasis in design for power has shifted with the advent of finFETs: “With the prior planar nodes, leakage was becoming more and more a concern. At 16nm leakage is now quite good. But the active power has gone up substantially just because of the gate capacitance of the finFETs. That is a tradeoff that we are working with and, internally, we are developing some techniques to deal with it. One of the great enablers of 16nm is that its voltage range is tremendous.”

Lahiri said: “We could never have imagined the number of voltage domains that we have to support for 16nm finFET [cell libraries]. It means much more simulation. And the more views that we need to generate puts stress on our compute resource.”

Raj Khanna, lead CPU developer at Soft Machines, agreed: “The gate capacitance is the big deal as far as active power is concerned. We are developing internal things to do much better slack management and deoptimization of things that are not critical. That extends all the way to libraries. There is a lot of wasted gate capacitance in multilevel cells. It doesn’t affect timing but it adds up in power.”

Paul Cunningham, R&D vice president at Cadence, said: “With increasing gate capacitance, you see a resurgence of things that used to have a lot of traction at 130nm. There was a very intensive focus on aggressive clock gating then.”

Even foundries were careful to not introduce too many changes and take too many risks in the move to finFETs. Quan called the two-step path to finfETs via the 20SOC process a risk-mitigation strategy. He said: “We didn’t want to jump to finFETs straight away with both finFET and double-patterning.”

Routing effects combine

However, the finFET and interconnect characteristics are working together to create additional problems, particularly for custom circuits and power distribution.

Khanna said: “16nm is a challenge for the industry, especially if youare doing full-custom design. On the custom side, the main realization has been that it’s nearly impossible today to predict the performance of a full custom design early on at the schematic level. You have to accelerate the path to layout, which means automation: more automatic routers that operate at a custom level.

“There are so many effects that operate on a proximity basis,” Khanna said, which causes issues as the project progresses: “If I tell the CTO that I will hit a target and it turns out to be off by 20 per cent, that’s a problem.”

Montaz said: “You had this at 40 and 28nm before. But the impact of the surroundings is getting greater and greater. The transistor to the side never made a difference before. Now they are. In your p-cell you put those effects in there so even on the schematic you are predicting how they will look post-layout.”

Interconnect performance has a further effect, Khanna said: “There is a substantial difference between 28nm and 16nm, especially at M0. And there has been a big effect on power distribution at the last mile.”

The need for high-capacity power routing into transistors that can require higher power density at a local level than their planar predecessors creates a bigger problem in terms of being able to hook up logic cells to their inputs and outputs. The result is that it can be difficult to achieve the desired performance and density – as one may have to give way to the other.

Khanna suggested that the emphasis in synthesis and place-and-route algorithms need to change to consider interconnect first. Paras Gupta, principal engineer at Qualcomm, agreed: “We lose a lot of performance to the routing. CPU design is going to be a big challenge going down [the process curve]. Wire resistance is really taking over: it’s now 50 per cent of the delay.”

FinFET cost choices

The considerations of chip cost, compute cost and design burden is shifting how companies approach the upcoming nodes. Lahiri said that with the current cost structure, driven particularly by the higher capital cost associated with double patterning, 16nm finFET is justified for server and other high-end processors and premium mobile but not for more cost-sensitive markets.

McCormack said: “Moore’s Law is continuing but it’s changing in terms of the cost structure. How do we provide value and get it on the market is becoming something of an art. We are definitely seeing power and frequency improvements for the next nodes. But the cost is a whole new game. And it’s changing how you think about how you position your parts and how you design your parts.”

Montaz agreed: “Many products will not go to the new nodes; they will probably stop where they are.”