Six ways to exploit the advantages of finFETs
FinFET processes and libraries are maturing, enabling designers to explore the best ways to take advantage of the capabilities of the new transistor design
dynamic power optimization
Placement optimizations push power and clock on Cortex-M7 project
Soft blocking to prevent cell spreading and other placement-optimization techniques helped improve power and clock speed on a Cortex-M7 test chip designed by ARM and Cadence.
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