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IoT device makers should play more with their software and make use of techniques used in website design to increase overall usability, Amazon’s head of IoT analytics has claimed.

Cadence Design Systems has made a collection of its tools suitable for cloud computing, providing them for both Cadence- and customer-managed environments.

Foundries have taken aim at standard-cell track height and design-rule tweaks to try to improve the area efficiency and performance of derivative finFET processes.

Deal to buy functional safety specialist builds out the automotive and Industry 4.0 offerings for Mentor and its parent Siemens.

At VLSI Symposia 2018, GlobalFoundries researchers proposed looking at the metal-gate ‘gear’ ratio as a way of improving the routability of standard cells.

For nVidia chief scientist and Stanford professor Bill Dally, now is a great time to be involved in hardware design, thanks to the rise of AI.

Real Intent's move into post-synthesis CDC debug leads its DAC 2018 activities, with technical papers on its new Verix PhyCDC tool also now online for those who cannot make it.

The portable stimulus pioneer will demonstrate how the technology and standard have been leveraged for its new Trek5 release.

Despite the intense R&D going into storage-class and other novel forms of non-volatile memories, flash is set to continue as the bulk memory of choice, Micron executive claims in VLSI Symposia keynote.

Researchers from the UC Berkeley and Intel teamed up to develop an energy-tuneable RF front-end on a digital finFET process with no need for analog process options.