System-level design meets power

By Chris Edwards |  1 Comment  |  Posted: February 27, 2012
Topics/Categories: Commentary, Conferences, Blog - EDA  |  Tags: , , , , ,

Reinhard Ploss, director of operations, R&D and labor at Infineon Technologies, gave an alternative view on system-level design to the one we normally see in the SoC world at SEMI’s ISS Europe conference in Munich, Germany on Monday and underlined why it’s hard to go fabless in the world of power semiconductors.

“In power semiconductors, you can’t separate [process] technology from the product,” Ploss argued, especially now when new materials are threatening to take over from bulk silicon. One option is gallium arsenide, he said. “But it is not quite there. Silicon carbide is already providing results despite the fact that the substrate is still very expensive, and its future is not a given.”

As a result, Ploss said, power semiconductor makers such as Infineon need to keep a close eye on the various substrate materials that could make a difference. “You have to invest a lot in R&D,” he said.

But the process changes can make dramatic differences to system-level performance, Ploss explained. “Companies making motor drives are the heavy-metal guys of the industry,” he said. The power electronics circuits need big heatsinks, take up a lot of space as a result and chew through a lot of power.

“But when you change the system architecture, you can reduce by 90 per cent the total size of a motor drive and save a lot on material cost,” said Ploss describing a new design based on silicon carbide junction field-effect transistors (JFETs) that run at 2.5 times the frequency of older silicon insulated gate bipolar transistors (IGBTs). The silicon carbide devices run happily at a junction temperature of more than 150°C, which saves massively on heatsink surface area. The higher switching frequency makes it possible to run the drive without large DC capacitors and with smaller filters and chokes. The peak power handling capacity increased tenfold to almost 20kW/l.

Ploss said the company is realising further space savings from system-in-package (SIP) techniques, using an approach the company calls Blade. This puts the power-handling and control devices into the same SIP. Because wiring becomes a limiting factor in power electronics circuits, SIP provides better electrical and thermal performance and the manufacturing technique that the company employs makes it possible to process multiple products in parallel on large panels – conceptually similar to LCD manufacture.

The devices themselves are making more use of 3D techniques, Ploss explained. “The roadmap for power devices is not the linear shrink you find in CMOS technology. Devices are structured on both the front and back side of the wafer: our next step is to integrate the IGBT and the diode. The diode goes on the backside. This means you have to make the chip very thin.”

In principle, as with CMOS, a move to larger wafers should help with cost. But there are issues when it comes to dealing with thin-wafer power devices.

“We have manufactured the first 300mm wafers for IGBT,” said Ploss, showing a picture of a wafer in a protective case. Removed from the case, the foil-like wafer buckled under the stresses imposed on the wafer by the various front and back-end processes. “The stresses make the wafer bend by itself. You have to think about ways to handle these wafers to prevent this from happening.

“Why do we do manufacturing by ourselves?” Ploss asked. “Because we have to. If someone else does it for you, you have to give your IP away. But this is why Europe has a differentiator in this area: because manufacturing competence matters as well as design.”

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