NI aims to bring design and production closer with chip-test plan
National Instruments plans to build an ecosystem around semiconductor test that could provide a missing link between the design process and production.
test
Formal app looks for sneak paths in secure chips
Jasper Design Automation has developed a tool that analyzes RTL and gate-level HDL for hidden paths that may expose on-chip secure elements to hackers.
3D-IC focus for GSA’s Taipei Memory+ event next week
Packed one-day event has speakers from Cadence, TSMC, Samsung, Amkor, Advantest and more providing a senior level view of making 3D-IC a reality. Registration closes soon.
Real Intent-DeFacTo sign-off flow for RTL combines CDC and DFT
Real Intent and DeFacTo Technologies combine clock-domain crossing and design for test tools in RTL sign-off flow.
IJTAG: delivering an industry platform for IP test and integration
Mentor's Stephen Pateras explains how the proposed IJTAG standard speeds IP test by replacing time-consuming custom and ad hoc methodologies.
ISQED focuses on systems, education and sensors
The International Symposium on Quality Electronic Design (ISQED) enters its 13th edition later this month, running March 19-21 at Techmart in Santa Clara. Although ISQED traditionally concentrated on tools and IP blocks, its agenda has broadened as the industry has migrated to SoCs and full electronic systems where process and manufacturing interactions have come to […]