Finding and fixing faults in finFET memories

By Yervant Zorian |  1 Comment  |  Posted: October 10, 2014
Topics/Categories: IP - Assembly & Integration, EDA - DFM, DFT  |  Tags: , , , ,  | Organizations:

Dr Yervant Zorian, SynopsysDr Yervant Zorian is the chief architect at Synopsys for embedded test and repair products. He has been a distinguished member of technical staff at AT&T Bell Laboratories, vice president and chief scientist of Virage Logic and chief technologist at LogicVision.

Although finFETs were invented in the 1990s, it is only recently that they have emerged as the key to meeting the stringent power and high-performance requirements of today’s complex SoCs. Freedom from the short-channel effects that have limited the scalability of planar devices has made finFETs even more attractive to designers and enabled Moore’s Law to continue.

The distinguishing characteristic of the finFET transistor is that the conducting channel consists of thin vertical silicon fins surrounded by gate electrodes. This leads to better control of the channel and better electrostatic properties, diminishing leakage current in the Off state, which greatly reduces short-channel effects. Due to their shape, finFETs have several advantages including controlled fin body thickness, low threshold-voltage variation, reduced variability and lower operating voltage, all of which help enable designs that can operate faster with less power.

Despite the significant power and performance benefits, finFET design and manufacturing introduces additional challenges. The novelty of the technology and the expected increase in manufacturing costs makes it worth taking a closer look at defects that could affect product quality and yield. This is a nontrivial task, given that even memories designed in advanced planar technologies can be affected by over 200 different defect types, each categorized as a unique fault model. It’s critical to develop a comprehensive yet optimized suite of test algorithms that detect these defects while keeping test cost low.

Although many of the defect types affecting memories based on planar transistors also affect finFET-based memories, new defects can occur due to the unique finFET structure. FinFET-based memories may also be less susceptible to certain defects that would cause failures in planar-based memories. Given these differences, the fault models and detection techniques developed for planar transistors are not sufficient to cover finFET defects in embedded memories.

Sample defects in finFETs (Source: Synopsys)

Figure 1 Sample defects in finFETs (Source: Synopsys)

Below are a few examples of defect types that could affect an embedded memory designed with finFETs (Figure 1).

  1. Fin Open – full and resistive open defects on fin
  2. Gate Open – full and resistive open defects on gate
  3. Fin Stuck-On – full and resistive short defects between source and drain
  4. Gate-Fin Short – full and resistive short defects
  5. Process Variation – variations in finFET parameter values

As with any new process node, Synopsys applies a rigorous approach to analyzing fault models, by injecting defects into the physical description of memories and then developing comprehensive test algorithms to detect all the resultant memory defects. This involves running numerous physical simulations to validate test algorithm effectiveness.

Maximizing yield is also an important consideration. To do this, repairable memories, which include redundancy and reconfiguration logic, are used. Efficient redundancy-allocation algorithms are also developed and validated. Once an optimal set of test and repair algorithms is established, they are encapsulated within a test and repair IP engine.

This test and repair IP has been validated in silicon on several real finFET-based embedded memories provided by leading silicon manufacturers (IDMs and foundries) [1,2,3]. This extensive silicon validation confirmed the presence of identified defects in finFET-based memories. Among other results, it showed that finFET-based memories are more prone to dynamic faults and less susceptible to process variation faults [4]

Chip designers using embedded finFET memories can take advantage of these advanced test and repair capabilities by using the Synopsys DesignWare STAR Memory System [5].

This is a comprehensive, embedded test, repair and diagnostics IP that supports repairable or non-repairable embedded memories. It provides test algorithm programmability, advanced memory addressing, programmable memory background patterns, and programmable test operations (Figure 2). These embedded capabilities are necessary to enable optimized test coverage. The algorithms detect not only static and dynamic faults, but also process variation and resistive faults.

The STAR Memory System can detect finFET-specific faults in memories provided by multiple silicon manufacturers. Its automated design implementation flow enables SoC designers to reduce design cycle times. A Silicon Browser and Yield Accelerator provide a seamless and efficient diagnostic flow for more efficient SoC bring-up to cut time to market, and to yield in volume production.

DesignWare STAR Memory Test and Repair architecture (Source: Synopsys)

Figure 2 DesignWare STAR Memory Test and Repair architecture (Source: Synopsys)

Further information

Yervant Zorian, Synopsys Fellow and chief architect of test IP products, will present an invited paper entitled Design, Test & Repair Methodology for finFET-based Memories at the International Test Conference 2014 (register here).

This presentation will discuss the design complexity, defect coverage and yield challenges of finFET-based memories and introduce new methods to address them. This will include new design techniques, new finFET-specific defects and their coverage, as well as yield optimization infrastructure.


  1. Synopsys and TSMC Collaborate to Validate DesignWare IP in TSMC 16-nm finFET Process. (2014). [online] Available at: [Accessed 2 Oct. 2014].
  2. Synopsys Accelerates Adoption of finFET Technology with Delivery of Production-Proven Design Tools and IP. (2014). [online] Available at: [Accessed 2 Oct. 2014].
  3. Samsung and Synopsys Collaborate to Achieve First 14-nanometer finFET Tapeout. [online] Available at: [Accessed 2 Oct. 2014].
  4. G. Harutyunyan, G. Tshagharyan, V. Vardanian, Y. Zorian, “Fault Modeling and Test Algorithm Creation Strategy for finFET-Based Memories”, IEEE VLSI Test Symposium, 2014, pp. 49-54. Available at: [Accessed 2 Oct. 2014].
  5. K. Darbinyan, G. Harutyunyan, S. Shoukourian, V. Vardanian, Y. Zorian, “A Robust Solution for Embedded Memory Test and Repair”, IEEE Asian Test Symposium, 2011, pp. 461-462. Available at:[Accessed 2 Oct. 2014]. 


Dr Yervant Zorian is the chief architect at Synopsys for embedded test and repair products, and is based in Mountain View, California.

Formerly, he was a distinguished member of technical staff at AT&T Bell Laboratories, vice president and chief scientist of Virage Logic and chief technologist at LogicVision. He received an MS degree in computer engineering from University of Southern California, a PhD in electrical engineering from McGill University, and an MBA from Wharton School of Business, University of Pennsylvania.

He is currently the president of IEEE Test Technology Technical Council (TTTC), the vice general chair of Design Automation Conference (DAC), the editor-in-chief wmeritus of Design & Test of Computers, the founder and chair of IEEE 1500 standardization working group, and an adjunct professor at University of British Columbia.

Company info

Synopsys Corporate Headquarters
700 East Middlefield Road
Mountain View, CA 94043
(650) 584-5000
(800) 541-7737

Comments are closed.


Synopsys Cadence Design Systems Siemens EDA
View All Sponsors