The evolution of the IC design process, coupled with exponential growth in design rules, has impacted design closure. It has become more difficult and time-consuming than ever to achieve tapeout on schedule (Figure 1). We have reached a point where signoff design rule checking (DRC) guidance during the design phase has become essential. The old-fashioned methodology for design closure is simply not meeting the demands set by the latest manufacturability rules. Instead of just one iteration for DRC and timing fixes, designers now must run multiple painful, time-consuming iterations.
Most of the time, this occurs because the routing rules the routers rely on are less complete than the signoff deck. The complexity of some signoff design rules creates a verification gap, meaning a design that is DRC-clean in place and route (P&R) can report many violations with a signoff run. While the routers might eventually catch up as a process node matures, that makes for a lot of wasted time and overrun schedules in-between. Giving designers the capability to interactively check for signoff DRC and get faster feedback during implementation can alleviate some of the challenges in DRC closure and ensure tapeout schedules are achieved.
EDA suppliers have responded to this need by providing tools that support interactive signoff DRC checking within the design environment. For example, the Calibre RealTime Digital interface from Siemens EDA provides fast, incremental signoff DRC checking and immediate feedback in the vicinity of the shapes being edited. Because Calibre RealTime Digital calls Calibre analysis engines interactively and runs checks using the signoff Calibre rule deck, designers can be confident that the fixes and optimizations they apply will be DRC-clean at closure. And, because the Calibre RealTime Digital interface is integrated with all major P&R tools, design companies can adopt an in-design signoff DRC process without having to change current flows.
While using the Calibre RealTime Digital interface provides instant time savings by eliminating many of the iterations previously needed for DRC closure, it also enables designers to improve layout quality by implementing layout optimizations during implementation. Floorplanning is a critical stage; any problems or deficiencies here can affect the entire design flow. So creating a floorplan optimized to meet PPA goals is essential.
Calibre RealTime Digital feedback can help designers get to that optimum floorplan with confidence. For example, as pins and macros are placed, designers can run Calibre signoff DRC interactively through the tool’s interface to ensure none of the placements create DRC errors. As an added benefit, designers no longer have to fix signoff DRC errors using sub-optimal options after implementation or encounter unpleasant surprises during the later stages of the design.
Faster signoff DRC convergence
DRC fixing can be a nightmare at advanced process nodes, with complicated checks and no routing resources. Physical design engineers typically spend weeks manually fixing the violations that the router has left behind. For example, when fixing a G0 violation, it often takes multiple iterations to make sure the edits hold, because any changes to the routes and/or shapes can trigger other violations. In such cases, waiting for a batch DRC run to find out the edits were not good enough is frustrating and time-consuming. Using the Calibre RealTime Digital interface, engineers can run Calibre signoff DRC on a region to validate the fix with one click (Figure 2).
The Calibre RealTime Digital flow also gives engineers the flexibility to run a full DRC deck on a window/area/cell, or just a subset of checks. Often, running all checks uses unnecessary time and resources. In the example shown in Figure 2, engineers can create ‘check recipes’ that run only M2 checks, since the focus is only on M2.G0 violations. Within a matter of seconds, engineers get valuable feedback on specific layout issues, saving them a lot of time and relieving their anxiety from seeing a huge list of unrelated or irrelevant DRC violations.
Managing the increasing complexity of the physical implementation of ICs is a crucial challenge as semiconductor companies accelerate their move to advanced process nodes. The Calibre RealTime Digital in-design verification solution enables engineers to get immediate signoff DRC feedback on targeted window-based DRC fixes, helping them achieve faster signoff DRC closure, meet critical milestones, and get to tapeout within their planned schedules.
The Calibre RealTime Digital interface enables P&R engineers to spend less time in DRC, so that they can focus on producing high-quality, optimized designs while still meeting ever-tighter production schedules. Because they can now iterate through signoff-quality DRC in the implementation environment, engineers can also be confident that the high-performance designs they create will meet all manufacturing requirements.
For more information, download the whitepaper Tape out on time with on-demand signoff DRC in P&R.