place and route

February 21, 2013

ISSCC 2013: AMD constraints help tame Jaguar

Some conservative decisions were important parts of AMD's design strategy for the 28nm core that's just been specified in PlayStation 4
Article  |  Topics: Blog - EDA, - Verification  |  Tags: , ,   |  Organizations:
October 11, 2012

The physical design challenges of 20nm processes

Manufacturability, routing, library design and more - it all needs rethinking at 20nm
Article  |  Topics: Design to Silicon, Blog - EDA, - Industry Blogs  |  Tags: , , , ,   |  Organizations:
April 24, 2012

Xilinx revamps design software for new processes

Xilinx has created Vivado, a new set of tools to support sub-30nm FPGAs that, for advanced designs at least, will take over from its long-established ISE suite.
Article  |  Topics: Commentary, Design to Silicon  |  Tags: , , , , , ,   |  Organizations:
March 15, 2012

CDN Live: Cadence’s Encounter revamp collates innovation

Performance boost claimed from streamlining optimization across synthesis and layout using modeling, novel CTS strategy and 20nm-ready features.

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