low power

Silicon Labs is aiming at Internet of Things applications with an ARM Cortex M0+-based MCU family with encryption engine and low-energy DAC for biasing analog circuitry.

The EDA vendor has set a broad agenda across two Silicon Valley events taking place in late October, with registration now open for both.

In a keynote at the Intel Developer Forum, CEO Brian Krzanich said the company would start making 14nm processors by the year end and confirmed intel would license SoC designs to be fabbed by other companies.

The group that developed the IEEE 1801 Unified Power Format standard is looking to bringing power modeling and estimation to the system level for version 3.0, due in 2015.

Sessions at the DAC 2013 conference in Austin, Texas focus on low-power design and engineering low-energy systems from the system level down to physical.

Vehicle-maker Volkswagen is putting its weight behind a set of microcontroller benchmarks that focus on energy consumption rather than performance.

Jasper Design Automation's modular concept moves into a hot area in SoC design to verify specs are still met after power management circuitry is inserted.

The fifth generation of Forte Design System's Cynthesizer tool is a slice of system-level evangelism.

Scale-out computing has demands so different from conventional applications that it could reshape the way to design one class of multicore processors.

With both now more dependent on foundry business for their finFET (trigate) and FDSOI offerings, DATE was a chance to push their innovations in low power.