Real Intent will release greatly extended Meridian CDC clock domain crossing software in November with new capabilities headlined by more hierarchical firepower and the launch of a user-configurable debugger.
The 2014.A edition announced today (September 30) will have 30% higher performance against the existing tool and a 40% smaller memory footprint, the company says. The formal analysis engine within Meridian has also been given a 10X lift in efficiency.
In a launch interview on YouTube, Ramesh Dewangan, vice-president of application engineering, says the built-out hierarchical flow is key to Meridian CDC’s capability (though the tool is equally capable of handling designs ‘flat’).
“[The hierarchical approach means that] the complete design view of the SoC is available for CDC analysis at any time. There is no abstraction or any approximation that is used that has a potential to miss bugs,” he says. Being more specific, there is neither abstract modeling nor waivers.
A new debugger for clock domain crossing
Real Intent says that the new debugger specifically leverages this hierarchical approach. Named iDebug (the ‘i’ standing for ‘intent’), it draws upon a Meridian CDC database that captures all phases of clock domain crossing verification for a hierarchical analysis of the design’s intent.
The iDebug software identifies root causes and then presents issues to users in an easy-to-assess and easy-t0-debug environment.
“[This is a] next generation debug environment,” says Dewangan. “It has an integrated GUI and has user-configurability and programmability using command line interfaces.
“All the CDC analysis data is stored in a database that can be accessed through CLI. So users are not stuck with one methodology that the tool provides for debug. Instead, they can create their own debug methodologies, custom to their own design flows which may include spreadsheet reports, may include some graphical reports or their own scripting. And so on.”
Run-time for clock domain crossing analysis
With recent envelope-pushing designs from AMD and nVIDIA both exceeding 5 billion gates, the tool has been designed to allow CDC checks to be undertaken at speed.
Dewangan says that the 40% decrease in memory and other performance improvements should mean that most projects can be run overnight “on a reasonable-sized machine”.
The new software will also have broader constraint support so that it can be used on a wider set of design types.