DAC2012: Collaboration key to success at 20nm

By Luke Collins |  No Comments  |  Posted: June 5, 2012
Topics/Categories: Conferences, Design to Silicon  |  Tags: ,  | Organizations:

The relationship between foundries, tool vendors and  customers is shifting, driven by the complexity of 28nm and 20nm design and manufacturing processes.

“As we go to 20nm it’s not a ‘good to have’, it’s a must,” said Mojy Chian, senior vice president, design enablement, GlobalFoundries. “I  believe there is an inflection happening in the foundry business and that inflection is the need for collaboration between foundry and customers. If they want to be successful they need to implement an IDM-like model through collaboration.

“Even at the early stages of process definition, because of the heavy interaction of design and manufacturing, we have to work together or we would not be able to get the benefits of the new processes. One design rule that has not been properly thought out could cut cell density by 5 or 10%.”

Chian says that GlobalFoundries is working closely with lead customers on technology definition for its 20nm process, discussing issues such as the metal pitch to use, the contact to poly pitch, which transistors to implement and how the design rules are defined.

“You have to look at DFM rules as a new generation of design rules,” he added. Design rules used to be all about proximity but now they are based on shapes as well. “These shape-based rules impact the way the layout is done. One thing we have seen at 28nm and 20nm is that we have to identify yield-limiting patterns and avoid them.”

These patterns can happen at the cell library level, where they can be picked up through early collaboration with the foundry.

“That’s another big component of why we need collaboration,” said Chian. It is also possible that forbidden patterns could emerge during the layout stage, and so GlobalFoundries can also analyse complete layouts to find and correct such problems.

The implementation of metal fill, which is used to help even out the effects of polishing steps in the process and to ease thermal gradients, is also becoming a collaborative process.

“Fill is not something that can be done in isolation by the custom or the foundry any more,” said Chian. “The more the customer knows about manufacturing requirements and the more we know about where the sensitive circuits are, the better. The fill process is never binary – customers can often not meet fab requirements  for fill so we ahem to work together to find a way around.”

Cost issues

Chian says there are cost challenges with 20nm processes, in the processing, the masks and the chip design process.

“What we see at 20nm is that the leading-edge manufacturers are moving to it as fast as possible but the mass of customers will not adopt it as quickly [as they did previous nodes], which will lead to an extension of the life of 28nm processes. The life of 28nm processes will be longer than previous nodes, and will overlap with 20nm for longer.”

Chian says GlobalFoundries’ 28nm process is now running in the Dresden fab and that the company has more than 90 tape-outs on the process, many of them production layouts targeted at 32nm and 28nm. The fab is at capacity and being expanded, says Chian.

“The good thing is end markets for our customers are improving and most leading edge customers don’t want to be single-sourced.”

The first full 20nm flow, base on process development done by the ISDA alliance, is now being ported to GlobalFoundries’ Fab 8 in New York. Chian says multi project wafer runs for test chips will start running on the 20nm process in June or July. He expects the company will do two or three more runs and then gear up for production in the first half of next year.

Will GlobalFoundries move from a planar transistor to a FinFET, in order to extend the lifetime of the 20nm process and avoid the uncertainty of moving to the next process node?

“It could be – we will have to see what the customer requirements and who the market shapes. But lithography is getting more challenging and so a lot of people will be looking at transistor engineering rather than going to the next design node.”

 

Leave a Comment

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors