Design to Silicon

June 5, 2012

DAC2012: Collaboration key to success at 20nm

Foundries can’t hand down design rules on tablets of stone any more - success at 20nm will take close collaboration with customers and tool vendors
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June 5, 2012

DAC 2012: ARM tips subthreshold power-gating technique

Could subthreshold circuitry help extend the reach of power gating? Mike Muller said during his DAC keynote that the technique looks viable.
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June 5, 2012

DAC2012: Sagantec offers lifebelt to 28nm users, path to 20nm libraries

Can process migration tools help the yield-challenged and speed the path to 20nm?
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June 4, 2012

DAC 2012: Google your way to DFM

The Silicon Integration Initiative (Si2) is targeting the end of the year for release 2.0 of its OpenDFM standard, which will include support for DRC+ and make it possible to build search engines for yield.
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June 1, 2012

DAC 2012: STMicro, Cadence, GlobalFoundries in 20nm AMS claims

The troops will be out in force next week to claim progress on 20nm AMS design flows that take manufacturability into account.
May 30, 2012

DAC 2012: Energetic Si2 finds time to look back

But as it celebrates a decade of OpenAccess, the standards body also looks toward the future in PDKs, advanced DFM and 3D.
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May 22, 2012

Making dummy fill smarter

Guest blogger Jeff Wilson discusses some of the subtleties involved in the effective use of dummy fill in deep sub-micron IC designs.
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May 14, 2012

Intel’s tapered fin reveals short-channel issues

A startup has analyzed the shape of Intel's fins and found the process is not quite as well-behaved as circuit designers would perhaps like.
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April 25, 2012

No more spaghetti

Cutting the cabling to simplify the emulation process.
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April 25, 2012

Mentor unveils second-generation Veloce emulator

Mentor Graphics has updated its Veloce emulator, using a newly developed chip to double capacity while, at the same time, developing new software to overcome the traditional handicaps of in-circuit emulation.
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