June 8, 2015
Google has moved to on-body tests of the the smart-lens platform it has been developing for the past few years while the team continues to experiment with embedded LEDs that react to blinks to help warn diabetes sufferers of sudden changes in glucose levels.
June 8, 2015
Following the acquisition of Jasper Design Automation last year, Cadence Design Systems is widening the target base of applications for formal verification, covering tasks from bug hunting through accelerated simulation to 'superlinting'.
June 8, 2015
Silicon Impulse program adds partners to ease industrialisation of ultra-low power IC designs based on FD-SOI processes
June 8, 2015
Altera is using a combination of Intel's 14nm process technology and multidie packaging to boost the logic-cell count for its FPGAs, together with a superpipelining strategy to help balance area and clock speed.
June 8, 2015
Gold Standard Simulations (GSS) has launched a tool intended to help fabless chipmakers squeeze more out of existing processes rather than accept the risk and expense of moving to more advanced, finFET-based processes.
June 8, 2015
Synopsys develops portfolio of ASIL B ready IP, and invests in AEC-Q100 testing and TS 16949 quality management, to ease automotive SoC qualification.
June 8, 2015
S3 Group has launched the second in a family of low-power successive-approximation ADCs, with a design that supports sample rates up to 320MS/s.
June 8, 2015
Atrenta's SpyGlass line and others to be absorbed in Verification Continuum and Galaxy as part of EDA's latest major consolidation.
June 7, 2015
IBM to offer end-to-end IC design flow on its own infrastructure in PAYG EDA model.
June 7, 2015
Invionics will be using its software environment to create a custom tool within just two days at the 52nd DAC.