Cadence uses machine learning to trim constrained-random runtimes
Cadence has developed a stimulus optimizer based on neural networks to try to improve the runtime of constrained-random verification runs.
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How to handle PCB constraints for IoT designs
An RF Laboratories engineer provides some tips and techniques in the context of the PADS Professional suite.
Open-RAN puts more focus on emulation in testing programs
Recent developments have made Open-RAN look more attractive as a way of implementing 5G systems. This is helping to drive a shift-left in verification and test.
Open and proprietary verification tools home in on RISC-V core quality
DAC provided a forum for the growing number of verification efforts focused on checking the architectural compliance and overall RTL quality of RISC-V processors.
Accellera IP security group expects standard by year end
The chair of Accellera’s IP security assurance working group expects the draft standard for hardening hardware core to be out by the end of the year.
DAC Pavilion focuses on cloud-scaling issues
Talks in the Design-on-Cloud Pavilion at this year’s DAC demonstrated how the question over its usage is not so much whether design could or should migrate to the cloud but how to optimize cost and performance when it’s there.
3D integration technologies will blend says TSMC chief scientist
DTCO and 3D integration will dominate scaling in the coming decade, TSMC chief scientist Philip Wong claimed in his keynote at DAC on Monday
Breker packages up apps for RISC-V, security and AI
Breker has added a number of specialized apps to its library that deal with the verification of RISC-V processors, secure enclaves, and machine-learning designs.
FastSPICE upgrade boosts nano-scale analog verification by up to 10X
Mentor adds Analog FastSPICE eXTreme innovations for designs facing increasing parasitic complexity and contact resistance challenges at cutting edge nodes.
Mentor tunes LVS for early SoC integration
Mentor has released a tool that attempts to deal with the problems encountered in the use of physical circuit verification in the early stages of SoC integration.