IMEC stacks nanowire transistors together on CMOS
Research institute IMEC has claimed at IEDM to have implemented for the first time the CMOS integration of vertically stacked gate-all-around (GAA) silicon nanowire MOSFETs.
GAA nanowire transistors are promising candidates to succeed FinFETs in 7nm and later technology nodes. They offer the best electrostatic control for a gate and, in a horizontal configuration, could provide a reasonably simple extension of today’s mainstream FinFET technology. Drive current through the nanowire is restricted but this can be increased by vertically stacking multiple horizontal nanowires. Earlier this year, IMEC researchers demonstrated GAA FETs based on vertically stacked 8nm-diameter silicon nanowires, but the n-channel and p-channel versions were fabricated separately.
IMEC said the key to the integration scheme is a dual-work-function metal gate enabling matched threshold voltages for the n- and p-type devices. First a p-type work-function metal is deposited in the gate trenches of all devices, followed by selectively etching the metal down to hafnium dioxide of the NFET’s gate, with a subsequent deposition of the n-type work-function metal. IMEC obtained a matched threshold voltage of 0.35V for types of transistor.
The work also studied the impact of the new architecture on intrinsic ESD performance. To deal with ESD issues, the team proposed two types of protection diode. One is a gate-structure defined diode and the other diode defined using shallow-trench isolation (STI). Experiments showed the STI diode to be the better ESD protection device. Measurements and TCAD simulations also prove that the ESD performance in GAA nanowire based diodes is maintained in comparison to bulk FinFET diodes.
“GAA nanowire transistors enable ultimate CMOS device scaling, with low degree of added complexity compared to alternative scaling scenarios,” said Dan Mocuta, director of logic device and integration at IMEC. “Future work will focus, among others, on further optimizing individual process steps, for example through the co-optimization of the junction and nanowire formation.”
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