EDA

Cliosoft sees a merging of social features and design-data repositories as driving more efficient reuse in chipmakers, bringing them together in its recently launched DesignHub product line.

Placement-aware synthesis and an array of post-layout recovery steps have helped drive up the clock speed and silicon utilization of a series high-end SoCs on leading-edge processes developed by customers of Synopsys' implementation tools.

An emulator that extends the reach of hardware acceleration into the world of multiphysics analysis could result from the merger of Siemens PLM Software with Mentor.

ARM has expanded its DesignStart program by providing access to the Cortex-M3 as well as the M0 with no up-front licence fee.

Former Cadence CEO tells DAC the IoT will lead to a burgeoning of chip design starts, followed by a brutal consolidation.

TSMC encapsulated the multiple chips assembled on a 1200mm2 silicon substrate to cut the chance of damage from warping with the company's CoWoS2 SiP technology.

EUV and fin optimization help build Samsung's upcoming 7nm process, the company discloses at the VLSI Technology Symposium.

Start-up Baum is co-located with Verific at DAC 2017 and will demonstrate its soon-to-launch power analysis and modeling software.

Accellera has released an Early Adopter version of the upcoming Portable Stimulus Specification.

At a DAC that will feature the arrival of the Accellera portable stimulus standard, Breker will demonstrate its implementation of the Early Adopter release of the specification.